The invention relates to power FETs (field effect transistors), and more particularly to gating circuitry for controlling a plurality of power FETs stacked in a series and parallel.
The stacking of power FETs is known. Stacking is the interconnection of multiple devices in configurations that result in capabilities beyond those of a single device. The present invention arose from efforts to develop gating techniques for a combination of two stacking techniques, series and parallel.
The stacking of multiple power FETs in parallel provides higher current capability, and lower ON resistance. Gating speed must be fast because the turn-on and turn-off transition time difference must be minimized.
The stacking of multiple power FETs in series results in higher voltage capability, and a better ratio of ON resistance to breakdown voltage. For example, connecting a pair of 100 volt devices in series results in a total voltage capability of 200 volts. The ON resistance in an individual power FET is proportional to the blocking voltage raised to the 2.6 power. Thus, doubling the blocking voltage in a single device results in an ON resistance which is increased more than six times. Stacking of a pair of devices in series affords the increased voltage blocking capability but with lower total ON resistance.
Various problems are encountered in the gating of series stacked power FETs, including voltage isolation and differing gate triggering levels. Each of the gates wants to reference to a different level, but it is desirable to drive all the gates from the same source via a single gate terminal.
The combination of parallel and series stacked power FETs affords both higher current capability and higher voltage capability, along with lower ON resistance. A plurality of power FETs are stacked in series until a given voltage rating is met. Additional groups of series stacked FETs are added in parallel until a given current rating and ON state resistance is met.
The present invention provides simple and efficient gating circuitry for controlling a set of series and parallel stacked power FETs.